1. Field of the Invention
The present invention relates to a dynamic memory, and more specifically to a dynamic memory is configured to transfer to a read-out signal line a read-out signal received to a gate of a transistor selected by a column selection signal in common to a plurality of memory cell arrays.
2. Description of Related Art
In dynamic memories such as a dynamic random access memory (DRAM), one means for speeding up the read-out operation is so configured that, when a read-out data on a bit line amplified by a sense amplifier is transferred to an output amplifier in a next stage, the read-out data is applied to a gate of a transistor, and then, transferred to the output amplifier. This configuration is disclosed by, for example, Y. Nakagome, et al., "An Experimental 1.5-V 64-Mb DRAM", IEEE Journal of Solid State Circuits, Vol. 26, No.4, page 465-472, April 1991, and S. Mori, et al., "A 45-ns 64-Mb DRAM with a Merged Match-Line Test Architecture", IEEE Journal of Solid State Circuits, Vol. 26, No.11, page 1486-1492, November 1991, the disclosure of both of which is incorporated by reference in their entirety into the present application. This configuration will be called a "gate receiving read-out circuit" hereinafter.
With reference to FIG. 1, one example of this type conventional dynamic memory will be now described.
This dynamic memory includes a plurality of memory cell arrays (MCA1, MCA2, . . . ), each of which includes a plurality of dynamic memory cells MC arranged in the form of a matrix having a plurality of rows and a plurality of columns, and a plurality of bit lines (for example, BL11 to BL16) each provided for each column of dynamic memory cells MC, for transferring a signal from the selected memory cell. The dynamic memory also includes a plurality of word lines (WL11, WL12, . . . , WL21, WL22, . . . ) for selecting a predetermined memory cell in a predetermined row in the plurality of memory cell arrays (MCA1, MCA2, . . . ), and a plurality of sense amplifiers (SA11, SA12, . . . , SA21, . . . ) provided one for each two columns of the plurality of memory cell arrays (MCA1, MCA2, . . . ), and activated at a predetermined timing in accordance with activation control signals SAP and SAN, so as to amplify a signal on a pair of bit lines.
Furthermore, the dynamic memory includes a plurality of data transfer circuits (DT11, DT21, DT22, . . . ) each located between one of the sense amplifiers (SA11, SA12, . . . , SA21, . . . ) and a corresponding memory cell array (MCA1, MCA2, . . . ) and configured to transfer a signal between the memory cell array and the sense amplifier at a predetermined timing in accordance with a data transfer signal (TG11, TG21, TG22, . . . ) and a plurality of read-out signal lines (DL11/DL12, DL21/DL22, . . . ) connected to the memory cell arrays (MCA1, MCA2, . . . ), respectively. In addition, the dynamic memory includes a plurality of selection read circuits (RC11, RC12, . . . , RC21, . . . ) of the gate receiving type, provided for the sense amplifiers (SA11, SA12, . . . , SA21, . . . ), respectively.
Each of the selection read circuits includes a pair of source-grounded first transistors Q1 and Q2 having their gate connected to receive a pair of complementary output signals of a corresponding sense amplifier, and a pair of second transistors Q3 and Q4 connected between a drain of the first transistors (Q1 and Q2) and a corresponding pair of read-out signal lines (DL11/DL12, DL21/DL22, . . . ), gates of the second transistors Q3 and Q4 being connected to receive a column selection signal (YS1, YS2, YS3, . . . ) in common to the memory cell arrays for controlling connection between the drain of the first transistors (Q1 and Q2) and the corresponding pair of read-out signal lines (DL11/DL12, DL21/DL22, . . . ). When the column selection signal is at a selection level, the selection read circuit transfers an amplified signal of the corresponding sense amplifier to a corresponding read-out line.
Moreover, the dynamic memory includes a plurality of load circuits (LD1, LD2, . . . ) provided for the read-out signal lines (DL11/DL12, DL21/DL22, . . . ), respectively, and including a pair of third transistors Q5 and Q6 connected between a corresponding pair of read-out signal lines and a voltage supply voltage so as to function as a load of a corresponding selection read circuit, and a plurality of output amplifiers (DA1, DA2, . . . ) connected to amplify a signal on the read-out signal lines (DL11/DL12, DL21/DL22, . . . ), so as to output an amplified signal to an external.
In the above mentioned dynamic memory, the memory cells in odd-numbered columns in each row of the memory cell arrays (MCA1, MCA2, . . . ) are selected by odd-numbered word lines, and the memory cells in even-numbered columns in each row are selected by even-numbered word lines. The sense amplifiers, the selection read circuits and the data transfer circuits are alternatively located at a right side or a left side of each two columns of memory cell arrays, so that the sense amplifiers, the selection read circuits and the data transfer circuits positioned between two adjacent memory cell arrays, are used in common to these two adjacent memory cell arrays. Therefore, a shared sense-up type of dynamic memory is constituted, so that an overall arrangement of the dynamic memory is as shown in FIG. 2.
In FIG. 2, each sense amplifier/selection read circuit SAR1 to SAR5 includes the sense amplifiers, the selection read circuits, the data transfer circuit, the read-out signal lines, the load circuit and the output amplifier.
Now, operation of this conventional dynamic memory will be explained with reference to a timing chart of FIG. 3.
For example, if the word line WL11 is brought to a selection level in response to a given row address signal (not shown), a voltage difference based on data stored in the memory cells connected to the word line WL11, appears between the respective pairs of bit lines (BL11/BL12, BL13/BL14, BL15/BL16, . . . ) of the memory cell array MCA1, which were set to an intermediate level between a high level and a low level. The voltage difference is transferred through the data transfer circuit DT11 to the sense amplifiers SA11, SA12. If the sense amplifiers are activated by the activation signals SAP and SAN, the transferred voltage difference is amplified by the sense amplifier to a difference between a voltage supply voltage level and a ground potential level.
Thereafter, if one of the column selection signals, for example, YS1 is brought to a selection level, the signal amplified by the sense amplifier (SA11) is transferred through the selection read circuit RC11 to the read-out signal lines DL11/DL12, and further, amplified by the output amplifier so as to be outputted to the external.
In the above mentioned dynamic memory, since the column selection signals (YS1, YS1, YS3, . . . ) are in common to a plurality of memory cell arrays (MCA1, MCA2, . . . ), the bit lines of the memory cell arrays which do not include the selected memory cells, and the input/output terminals of the corresponding sense amplifiers remain at the intermediate potential level. Because of this, the transistors Q1 and Q2 in the corresponding read selection circuit are turned on, so that a voltage supply current flows through the transistors Q5 and Q6 of the load circuit, the transistors Q3 and Q4 of the selection read circuit, and then, the transistors Q1 and Q2 of the selection read circuit. As a result, a consumed electric power is increased.
It is possible to block the above mentioned voltage supply current, by inserting a ground controlling transistor between the source of the transistors Q1 and Q2 and the ground, and by turning on only the ground controlling transistor corresponding to the memory cell array including the selected memory cells. However, this approach is not satisfactory for the following reason: Since the sources of the transistors Q1 and Q2 of many selection read circuits are connected in common to each other, the sources of the transistors Q1 and Q2 have a large parasitic capacitance. In addition, the parasitic capacitance are charged to a level near to the voltage supply voltage through the selection read circuit corresponding to the column selection signal of the selection level. Furthermore, the ground controlling transistor is set to have a large a current driving capacity, for the purpose of preventing a floating of the source potential of the transistors Q1 and Q2 in the selected circuit (lowering of the reading voltage), and for realizing a high speed operation. Accordingly, when the selection read circuit is brought from a non-selected condition to a selected condition, a large current (particularly having a large peak value) flows through the ground controlling transistor. This large current gives an adverse influence to the other circuits.